SH7014 datasheet(35/754 Pages) RENESAS

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1. SH7014/16/17 Overview

Rev.5.00 Sep. 27, 2007 Page 1 of 716

REJ09B0398-0500

Section 1 SH7014/16/17 Overview

1.1

SH7014/16/17 Overview

The SH7014/16/17 CMOS single-chip microprocessors integrate a Renesas Technology-original

architecture, high-speed CPU with peripheral functions required for system configuration.

The CPU has a RISC-type instruction set

. Most instructions can be executed in one clock cycle,

which greatly improves instruction execution speed

. In addition, the 32-bit internal-bus

architecture enhances data processing power. With this CPU, it has become possible to assemble

low cost, high performance/high-functioning systems, even for applications that were previously

impossible with microprocessors, such as real-time control, which demands high speeds. In

particular, the SH7040 series has a 1-kbyte on-chip cache, which allows an improvement in CPU

performance during external memory access.

In addition, this LSI includes on-chip peripheral functions necessary for system configuration,

such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial

communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory

or peripheral LSIs can be connected efficiently with an external memory access support function.

This greatly reduces system cost.

This LSI has an F-ZTAT

TM* version with on-chip flash memory and a mask ROM version. These

versions enable users to respond quickly and flexibly to changing application specifications,

growing production volumes, and other conditions.

Notes: F-ZTAT (Flexible ZTAT) is a trademark of Renesas Technology Corp.

1.1.1

SH7014/16/17 Series Features

CPU:

• Original Renesas Technology architecture

• 32-bit internal data bus

• General-register machine

⎯ Sixteen 32-bit general registers

⎯ Three 32-bit control registers

⎯ Four 32-bit system registers

• RISC-type instruction set

⎯ Instruction length: 16-bit fixed length for improved code efficiency

⎯ Load-store architecture (basic operations are executed between registers)

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