SH7014 datasheet(70/754 Pages) RENESAS

70 / 754 page

2. CPU

Rev.5.00 Sep. 27, 2007 Page 36 of 716

REJ09B0398-0500

Table 2.11

Instruction Code Format

Item

Format

Explanation

Instruction

OP.Sz SRC,DEST

OP: Operation code

Sz: Size (B: byte, W: word, or L: longword)

SRC: Source

DEST: Destination

Rm: Source register

Rn: Destination register

imm: Immediate data

disp: Displacement*1

Instruction

code

MSB

↔ LSB

mmmm: Source register

nnnn: Destination register

0000: R0

0001: R1

1111: R15

iiii: Immediate data

dddd: Displacement

Operation

→, ←

Direction of transfer

(xx)

Memory operand

M/Q/T

Flag bits in the SR

Logical AND of each bit

Logical OR of each bit

Exclusive OR of each bit

Logical NOT of each bit

<<n

n-bit left shift

>>n

n-bit right shift

Execution

cycles

⎯

Value when no wait states are inserted*2

T bit

⎯

Value of T bit after instruction is executed. An em-dash (

⎯)

in the column means no change.

Notes: 1. Depending on the operand size, displacement is scaled

×1, ×2, or ×4. For details, see

the SH-1/SH-2/SH-DSP Software Manual.

2. Instruction execution cycles: The execution cycles shown in the table are minimums.

The actual number of cycles may be increased when (1) contention occurs between

instruction fetches and data access, or (2) when the destination register of the load

instruction (memory

→ register) and the register used by the next instruction are the

same.

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