SH7014 datasheet(26/754 Pages) RENESAS

26 / 754 page

Rev.5.00 Sep. 27, 2007 Page xxvi of xxxiv

REJ09B0398-0500

10.4.7 Phase Counting Mode .......................................................................................... 244

10.5

Interrupts ........................................................................................................................... 251

10.5.1 Interrupt Sources and Priority Ranking................................................................ 251

10.5.2 DMAC Activation................................................................................................ 252

10.5.3 A/D Converter Activation.................................................................................... 252

10.6

Operation Timing.............................................................................................................. 253

10.6.1 Input/Output Timing ............................................................................................ 253

10.6.2 Interrupt Signal Timing........................................................................................ 258

10.7

Usage Notes ...................................................................................................................... 262

10.7.1 Input Clock Limitations ....................................................................................... 262

10.7.2 Note on Cycle Setting .......................................................................................... 262

10.7.3 Contention between TCNT Write and Clear........................................................ 263

10.7.4 Contention between TCNT Write and Increment ................................................ 264

10.7.5 Contention between Buffer Register Write and Compare Match ........................ 265

10.7.6 Contention between TGR Read and Input Capture.............................................. 266

10.7.7 Contention between TGR Write and Input Capture............................................. 267

10.7.8 Contention between Buffer Register Write and Input Capture ............................ 268

10.7.9 Contention between TGR Write and Compare Match ......................................... 269

10.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 269

10.7.11 Contention between Overflow/Underflow and Counter Clearing........................ 271

10.7.12 Contention between TCNT Write and Overflow/Underflow............................... 272

10.7.13 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode 1....... 272

10.8

MTU Output Pin Initialization .......................................................................................... 273

10.8.1 Operating Modes.................................................................................................. 273

10.8.2 Reset Start Operation ........................................................................................... 273

10.8.3 Operation in Case of Re-Setting Due to Error during Operation, Etc.................. 273

10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error

during Operation, etc. .......................................................................................... 274

Section 11 Watchdog Timer (WDT).............................................................................. 291

11.1

Overview........................................................................................................................... 291

11.1.1 Features................................................................................................................ 291

11.1.2 Block Diagram..................................................................................................... 292

11.1.3 Pin Configuration................................................................................................. 292

11.1.4 Register Configuration......................................................................................... 293

11.2

Register Descriptions ........................................................................................................ 293

11.2.1 Timer Counter (TCNT)........................................................................................ 293

11.2.2 Timer Control/Status Register (TCSR)................................................................ 294

11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 296

11.2.4 Register Access.................................................................................................... 297

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