SH7014 datasheet(76/754 Pages) RENESAS

номер детали	SH7014

подробное описание детали	32-Bit RISC Microcomputer

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2. CPU

Rev.5.00 Sep. 27, 2007 Page 42 of 716

REJ09B0398-0500

Table 2.14

Logic Operation Instructions

Instruction

Instruction Code

Operation

Exec.

Cycles

T Bit

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm

→ Rn

⎯

AND

#imm,R0

11001001iiiiiiii

R0 & imm

→ R0

⎯

AND.B #imm,@(R0,GBR)

11001101iiiiiiii

(R0 + GBR) & imm

→

(R0 + GBR)

⎯

NOT

Rm,Rn

0110nnnnmmmm0111

∼Rm → Rn

⎯

Rm,Rn

0010nnnnmmmm1011

Rn | Rm

→ Rn

⎯

#imm,R0

11001011iiiiiiii

R0 | imm

→ R0

⎯

OR.B

#imm,@(R0,GBR)

11001111iiiiiiii

(R0 + GBR) | imm

→

(R0 + GBR)

⎯

TAS.B @Rn

0100nnnn00011011

If (Rn) is 0, 1

→ T; 1 →

MSB of (Rn)*

Test

result

TST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm; if the result is

0, 1

→ T

Test

result

TST

#imm,R0

11001000iiiiiiii

R0 & imm; if the result is

0, 1

→ T

Test

result

TST.B #imm,@(R0,GBR)

11001100iiiiiiii

(R0 + GBR) & imm; if

the result is 0, 1

→ T

Test

result

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm

→ Rn

⎯

XOR

#imm,R0

11001010iiiiiiii

R0 ^ imm

→ R0

⎯

XOR.B #imm,@(R0,GBR)

11001110iiiiiiii

(R0 + GBR) ^ imm

→

(R0 + GBR)

⎯

Note:

The on-chip DMAC bus cycles are not inserted between the read and write cycles of

TAS instruction execution.

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