SH7014 datasheet(16/754 Pages) RENESAS

16 / 754 page

Rev.5.00 Sep. 27, 2007 Page xvi of xxxiv

REJ09B0398-0500

Item

Page

Revision (See Manual for Details)

15.4.3 Compare Match

Flag Clear Timing

428

Description amended

The CMF bit of the CMCSR register is cleared either by writing

a 0 to it after reading a 1

. Figure 15.5 shows the timing

when the CMF bit is cleared by the CPU.

16.3.2 Port A Control

Registers L1, L2

(PACRL1 and PACRL2)

446

Description amended

PACRL1 is initialized by external power-on reset to H'4000 in

extended mode, and to H'0000 in single chip mode. PACRL2 is

initialized by external power-on reset to H'0000. Neither register

is initialized by reset by WDT, standby mode, or sleep mode, so

the previous data is maintained.

Description amended

Bit 14

PA15MD Description

General input/output (PA15)

(single chip mode initial value)

Port A Control Register

L1 (PACRL1):

Bit 14—PA15 Mode

(PA15MD):

447

Clock output (CK)

(extended mode initial value)

16.3.3 Port B I/O

452

Description amended

The port B I/O register L (PBIOR) is a 16-bit read/write register

that selects input or output for the ten pins of port B (eight pins

in the SH7014). Bits PB9IOR to PB0IOR correspond to the

PB9/

IRQ7/A21 pin to PB0/A16 pin. PBIOR is enabled when the

port B pins function as input/outputs (PB9 to PB0). For other

functions, it is disabled.

17.2.2 Port A Data

477

Description amended

PADRL is initialized by an external power-on reset. However,

PADRL is not initialized for a

reset by WDT, standby mode,

or sleep mode.

17.3.2 Port B Data

479

Description amended

PBDR is initialized by an external power-on reset. However,

PBDR is not initialized for a

reset by WDT, standby mode,

or sleep mode.

17.4.2 Port C Data

481

Description amended

PCDR is initialized by an external power-on reset. However,

PCDR is not initialized for a

reset by WDT, standby mode,

or sleep mode.

17.5.2 Port D Data

483

Description amended

PDDRL is initialized by an external power-on reset. However,

PDDRL is not initialized for a

reset by WDT, standby mode,

or sleep mode.

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