SH7014 datasheet(116/754 Pages) RENESAS

116 / 754 page

6. Interrupt Controller (INTC)

Rev.5.00 Sep. 27, 2007 Page 82 of 716

REJ09B0398-0500

As indicated in table 6.4, four

IRQ pins or groups of 4 on-chip peripheral modules are allocated to

each register. Each of the corresponding interrupt priority ranks are established by setting a value

from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0.

Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting

H'F. If multiple on-chip peripheral modules are assigned to WDT and BSC, those multiple

modules are set to the same priority rank.

IPRA to IPRH are initialized to H'0000 by a power-on reset. They are not initialized in standby

mode.

6.3.2

Interrupt Control Register (ICR)

The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input

pin NMI and

IRQ0 to IRQ3, IRQ6, IRQ7 and indicates the input signal level to the NMI pin. It is

initialized by power-on reset, but is not initialized by standby mode.

Bit:

NMIL

⎯

NMIE

Initial value:

R/W:

R/W

Bit:

IRQ0S

IRQ1S

IRQ2S

IRQ3S

⎯

IRQ6S

IRQ7S

Initial value:

R/W:

R/W

Note:

When NMI input is high: 1; when NMI input is low: 0

Bit 15

⎯NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can

be read to determine the NMI pin level. This bit cannot be modified.

Bit 15

NMIL

Description

NMI input level is low

NMI input level is high

Bits 14 to 9, 3, 2

⎯Reserved: These bits always read as 0. The write value should always be 0.

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