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M16C/29 датащи(PDF) 105 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 105 Page - Renesas Technology Corp |
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105 / 499 page ![]() 9. Interrupts p u o r G 9 2 / C 6 1 M page 81 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 9.7 shows the stack status before and after an interrupt request is accepted. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction. Figure 9.7 Stack Status Before and After Acceptance of Interrupt Request Address Content of previous stack Stack [SP] SP value before interrupt request is accepted. m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stack m + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address FLGL Content of previous stack Stack FLGH PCH [SP] New SP value Content of previous stack m + 1 MSB LSB PCL PCM |
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