M16CSLASH29 datasheet(103/499 Pages) RENESAS

103 / 499 page

9. Interrupts

page 79

9.4 Interrupt Sequence

An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the

interrupt routine is executed) is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

The CPU behavior during the interrupt sequence is described below. Figure 9.5 shows time required for

executing the interrupt sequence.

(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading

the address 0000016. Then it clears the IR bit for the corresponding interrupt to 0 (interrupt not

requested).

(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal

temporary register(Note).

(3) The I, D and U flags in the FLG register become as follows:

The I flag is cleared to 0 (interrupts disabled).

The D flag is cleared to 0 (single-step interrupt disabled).

The U flag is cleared to 0 (ISP selected).

However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is

executed.

(4) The CPU’s internal temporary register(1) is saved to the stack.

(5) The PC is saved to the stack.

(6) The interrupt priority level of the accepted interrupt is set in the IPL.

(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, the processor resumes executing instructions from the start

address of the interrupt routine.

NOTE:

1. This register cannot be used by user.

Figure 9.5 Time Required for Executing Interrupt Sequence

1112

1617

SP-2

contents

SP-4

contents

vec

contents

vec+2

contents

Interrupt

information

Address

000016

Undefined(1)

SP-2

SP-4

vec

vec+2

CPU clock

Address bus

Data bus

WR(2)

NOTES:

1. The undefined state depends on the instruction queue buffer. A read cycle occurs when the instruction queue

buffer is ready to accept instructions.

2. When the stack is in the internal RAM, the WR signal indicates the write timing by changing high-level to low-level.

Undefined(1)

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