M16CSLASH29 datasheet(8/499 Pages) RENESAS

8 / 499 page

A-1

Table of Contents

Quick Reference to Pages Classified by Address _____________________ B-1

1. Overview ____________________________________________________ 1

1.1 Features ........................................................................................................................... 1

1.1.1 Applications ................................................................................................................ 1

1.1.2 Specifications ............................................................................................................. 2

1.2 Block Diagram .................................................................................................................. 4

1.3 Product List....................................................................................................................... 6

1.4 Pin Assignments .............................................................................................................12

1.5 Pin Description ............................................................................................................... 18

2. Central Processing Unit (CPU) __________________________________ 21

2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 21

2.2 Address Registers (A0 and A1) ...................................................................................... 21

2.3 Frame Base Register (FB).............................................................................................. 22

2.4 Interrupt Table Register (INTB) ....................................................................................... 22

2.5 Program Counter (PC).................................................................................................... 22

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .......................................... 22

2.7 Static Base Register (SB) ............................................................................................... 22

2.8 Flag Register (FLG) ........................................................................................................ 22

2.8.1 Carry Flag (C Flag) .................................................................................................. 22

2.8.2 Debug Flag (D Flag)................................................................................................. 22

2.8.3 Zero Flag (Z Flag) ................................................................................................... 22

2.8.4 Sign Flag (S Flag) .................................................................................................... 22

2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 22

2.8.6 Overflow Flag (O Flag) ............................................................................................. 22

2.8.7 Interrupt Enable Flag (I Flag) ................................................................................... 22

2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 22

2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 22

2.8.10 Reserved Area ....................................................................................................... 22

3. Memory ____________________________________________________ 23

4. Special Function Registers (SFRs) _______________________________ 24

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