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M16C/29 датащи(PDF) 29 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 29 Page - Renesas Technology Corp |
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29 / 499 page ![]() 1. Overview page 5 p u o r G 9 2 / C 6 1 M 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 1.2 is a block diagram of the M16C/29 Group, 64-pin package. Figure 1.2 M16C/29 Group, 64-Pin Block Diagram Output (Timer A) : 5 Input (Timer B) : 3 Internal Peripheral Functions Watchdog timer (15 bits) DMAC (2 channels) Memory ROM(1) RAM(2) UART/Clock synchronous SI/O (8 bits x 3 channels) System clock generator XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer M16C/60 Series CPU Core R0L R0H R1H R1L R2 R3 A0 A1 FB SB ISP USP INTB Multiplier Port P2 8 PC FLG Timer (16 bits) 3-phase PWM Port P3 4 Port P1 3 I/O Ports Port P0 4 Timer S Input capture/ Output compare Time measurement : 8 channels Waveform generating : 8 channels Clock synchronous SI/O (8 bits x 1 channel) Multi-master I2C bus ( ) A/D converter (10 bits x 16 channels) CRC calculation circuit (CRC-CCITT, CRC16) CAN module (1 channel) NOTES: 1. The ROM capacity varies depending on each product. 2. The RAM capacity varies depending on each product. |
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