M16CSLASH29 datasheet(107/499 Pages) RENESAS

107 / 499 page

9. Interrupts

page 83

9.4.4 Returning from an Interrupt Routine

The FLG register and PC in the state in which they were immediately before entering the interrupt se-

quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.

Thereafter the CPU returns to the program which was being executed before accepting the interrupt

request.

Return the other registers saved by a program within the interrupt routine using the POPM or similar

instruction before executing the REIT instruction.

9.5 Interrupt Priority

If two or more interrupt requests are generated while executing one instruction, the interrupt request that

has the highest priority is accepted.

For maskable interrupts (peripheral functions), any desired priority level can be selected using bits ILVL2 to

ILVL0. However, if two or more maskable interrupts have the same priority level, their interrupt priority is

resolved by hardware, with the highest priority interrupt accepted.

The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.9

shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Reset

Watchdog timer, oscillation stop,

re-oscillation detection,

low voltage detection

Peripheral function

Single step

Address match

High

Low

NMI

DBC

Figure 9.9 Hardware Interrupt Priority

9.5.1 Interrupt Priority Resolution Circuit

The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those

requested.

Figure 9.10

shows the circuit that judges the interrupt priority level.

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