M16CSLASH29 datasheet(102/499 Pages) RENESAS

102 / 499 page

9. Interrupts

page 78

9.3.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (= enabled) enables the

maskable interrupt. Setting the I flag to 0 (= disabled) disables all maskable interrupts.

9.3.2 IR Bit

The IR bit is set to 1 (= interrupt requested) when an interrupt request is generated. Then, when the

interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is

cleared to 0 (= interrupt not requested).

The IR bit can be cleared to 0 in a program. Note that do not write 1 to this bit.

9.3.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0.

Table 9.3

shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels

enabled by the IPL.

The following are conditions under which an interrupt is accepted:

· I flag = 1

· IR bit = 1

· interrupt priority level > IPL

The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. In no case do they affect

one another.

Table 9.4 Interrupt Priority Levels

Enabled by IPL

Table 9.3 Settings of Interrupt Priority

Levels

ILVL2 to ILVL0 bits

Interrupt priority

level

Priority

order

0002

0012

0102

0112

1002

1012

1102

1112

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL

0002

0012

0102

0112

1002

1012

1102

1112

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