M16CSLASH29 datasheet(66/499 Pages) RENESAS

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5. Resets

page 42

Figure 5.8 Low Voltage Detection Interrupt Generation Block

Figure 5.9 Low voltage Detection Interrupt Generation Circuit Operation Example

Low voltage detection interrupt generation circuit

Watchdog

timer interrupt

signal

D42 bit is set to 0 (not detected) by

writing a 0 in a program. VC27 bit is

set to 0 (low voltage detection circuit

disabled), the D42 bit is set to 0.

VC27

VC13

Low voltage detection circuit

D4INT clock(the

clock with which it

operates also in

wait mode)

D42

DF1, DF0

1/2

002

012

102

112

1/2

1/8

Non-maskable

interrupt signal

Oscillation stop,

re-oscillation

detection

interrupt signal

Low voltage

detection

interrupt signal

Watchdog timer block

This bit is set to 0 (not detected) by writing a 0 by program.

Watchdog timer

underflow signal

D43

D41

CM02

WAIT instruction (wait mode)

D40

VCC

Vref

Noise

rejection

(Rejection wide:200 ns)

Low voltage detection

signal

“H” when VC27 bit = 0

(disabled)

Noise rejection

circuit

Digital

filter

CM10

Output of the digital filter (2)

D42 bit

Low voltage detection

interrupt signal

No low voltage detection interrupt signals are

generated when the D42 bit is 1.

sampling

Set to 0 by

program (not

detected)

VC13 bit

VCC

sampling

samplingsampling

Set to 0 by a

program (not

detected)

NOTES:

1. D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled).

2. Output of the digital filter shown in Figure 5.8.

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