M66596FP datasheet(116/131 Pages) RENESAS

116 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 116 of 127

Note 3-1: The inactive condition for DREQi_N (i=0, 1) is the control signal. If there is a next DMA transfer, the delay

ratings for twh (Dreq) and ten (CTRL-Dreq) will be valid for the time until DREQi_N becomes active is twh

(Dreq).

Note 3-2: The control signal when writing data is a combination of DACKi_N, WR1_N, and WR0_N.

Note 3-3: The control signal when reading data is a combination of DACKi_N and RD_N.

Note 3-4: The control signal when writing data is a combination of DACK0 and DSTRB0_N.

Note 3-5: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N.

Note 3-6: The control signal when reading data is a combination of CS_N and RD_N.

Note 3-7: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N

should not be timed to fall at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances

noted above, an interval of at least 10 ns must be left open.

Note 3-8: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that DACKi_N is rising (or falling).

Similarly, DACK should not be timed to fall (or rise) at the same timing that RD_N or WR0_N and WR1_N are

rising. In the instances noted above, an interval of at least 10 ns must be left open.

Note 3-9: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined

time is "(24)td(DREQ-DendV)".

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