M66596FP datasheet(30/131 Pages) RENESAS

30 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 30 of 127

2.7 Interrupts enabled

Interrupts enabled register 0[INTENB0]

<Address: 30H>

VBSE

RSME

SOFE

DVSE

CTRE BEMPE NRDYE BRDYE URST

SADR

SCFG

SUSP

WDST

RDST

CMPL

SERR

Bit

Name

Function

S/W

H/W

Note

VBSE

VBUS interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.8

3.2.9

RSME

Resume interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.8

3.2.10

SOFE

Frame number refresh interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

3.2.8

DVSE

Device state transition interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.2

3.2.6

CTRE

Control transfer stage t

ransition interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.3

3.2.7

BEMPE

Buffer Empty interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

3.2.5

NRDYE

Buffer Not Ready response interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

3.2.4

BRDYE

Buffer Ready interrupts enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

3.2.3

URST

Default state transition notifications enabled

0: DVST interrupt disabled at transition to

default state

1: DVST interrupt enabled at transition to

default state

R/W

2.7.2

3.2.6

SADR

Address state transition notifications enabled

0: DVST interrupt disabled at transition to

address state

1: DVST interrupt enabled at transition to

address state

R/W

2.7.2

3.2.6

SCFG

Configuration state transition notifications

enabled

0: DVST interrupt disabled at transition to

configuration state

1: DVST interrupt enabled at transition to

configuration state

R/W

2.7.2

3.2.6

SUSP

Suspend state transition notifications enabled

0: DVST interrupt disabled. at transition to

suspend state

1: DVST interrupt enabled at transition to

suspend state

R/W

2.7.2

3.2.6

WDST

Control write transfer status stage transition

notifications enabled

0: CTST interrupt disabled at transition to

status stage of control write transfer

1: CTST interrupt enabled at transition to

status stage of control write transfer

R/W

2.7.3

3.2.7

RDST

Control read transfer status stage transition

notifications enabled

0: CTST interrupt disabled at transition to

status stage of control read transfer

1: CTST interrupt enabled at transition to

status stage of control read transfer

R/W

2.7.3

3.2.7

CMPL

Control transfer end notifications enabled

0: CTST interrupt are disabled at end of

control transfer

1: CTST interrupt enabled at end of control

transfer

R/W

2.7.3

3.2.7

SERR

Control transfer sequence error notifications

enabled

0: CTST interrupt disabled at detection of

control transfer sequence error

1: CTST interrupt enabled at detection of

control transfer sequence error

R/W

2.7.3

3.2.7

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