M66596FP datasheet(54/131 Pages) RENESAS

54 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 54 of 127

3.1.7.4 Recovering from the low-power sleep state

If any of the events noted below occurs from the low-power sleep state, the controller notifies the CPU through the

INT_N

pin. The interrupt factor related to those events should be enabled, before sofware sets the controller to the

low-power sleep state.

VBUS detection

: If a change in the VBUS pin was detected in the low-power sleep state

RESUME detection

: If a change in the state of the USB bus (J-State to K-State or SE0)was detected

when the state shifted from the suspended state to the low-power sleep state in the

Peripheral mode.

BUS CHANGE detection : If a change in the state of the USB bus was detected when the state to the

low-power sleep state state during the suspended state

When the PCSE bit of INTENB1 register is set to "0", the low-power sleep state is also canceled by the operations

noted below, and the controller returns to the normal operating state.

Dummy writing to the 0x7E address of the controller (no actual writing is

done to this address).

When the system has returned from the low-power sleep state to the normal state, some of the controller registers

need to be returned to the values in effect prior to the transition to the low-power sleep state. Of the registers for

which the settings have to be returned, special registers are available that are used for re-setting data in the

read-only registers.

Table 3.6 shows the re-settings for the read-only registers for which the settings have to be returned.

Table 3.6 Re-settings for read-only registers for which settings have to be returned

Bit

Method for re-setting registers

DVSTCTR

RHST

INTSTS0

DVSQ

Setting the USB communication speed and device state using the STSRECOV bit

of the RECOVER register before shifting to the low-power sleep state recovers the

values for the RHST bit and DVSQ bit.

RECOVER

USBADDR

The USB device address prior to the shift to the low-power sleep state is set in the

USBADDR bit of the RECOVER register.

PIPExCTR

SQMON

The sequence toggle bits for the various pipes prior to the low-power sleep state

are set using the SQSET bit or the SQCLR bit of PIPExCTR. *1)

*1) The SQMON bit of the DCPCTR register is initialized when the SETUP stage ends, so it is not necessary to

return to the state in effect prior to the normal operating state.

3.1.7.5 Recovering from the clock stop state

If any of the events noted below occurs from the clock stop state, the controller notifies the CPU through the INT_N

pin. The interrupt factor related to those events should be enabled, before sofware sets the controller to the clock stop

state.

VBUS detection

: If a change in the VBUS pin was detected in the clock stop state.

RESUME detection

: In the suspended state of Peripheral mode if a change in the state of the USB bus

(J-State to K-State/SE0)was detected.

BUS CHAGE detection : If a change in the state of the USB bus was detected. It is used when detecting attach

a peripheral , detach a perripheral, and Remote Wake Up in the Host mode.

3.1.7.6 Auto clock supply function

This controller is equipped with an auto clock supply function. With the auto clock supply function, the controller

automatically implements a series of sequence control operations, from the oscillation stabilization standby timing to

the supply of the internal clock, when the system is returning from the low-power sleep state or from the clock stop

mode to the normal operating state. This function is enbaled by setting “1” for the ATCKM bit of the SYSCFG

3.1.8.3 .

RESUME detection

In the suspended state of Peripheral mode if a change in the state of the USB bus (J-State to

K-State/SE0)was detected.

If Software set “XCKE=1” of SYSCFG register.

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