M66596FP datasheet(35/131 Pages) RENESAS

35 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 35 of 127

2.9 Interrupt statuses

Interrupt status register 0[INTSTS0]

<Address: 40H>

VBINT

RESM

SOFR

DVST

CTRT

BEMP

NRDY

BRDY VBSTS

DVSQ

VALID

CTSQ

Bit

Name

Function

S/W

H/W

Note

15 VBINT

VBUS interrupt status

0: VBUS interrupts not issued

1: VBUS interrupts issued

R/W

3.2.9

3.2.10

*3)

14 RESM

Resume interrupt status

0: Resume interrupts not issued

1: Resume interrupts issued

R/W

3.2.10

*3)

13 SOFR

Frame number refresh interrupt status

0: SOF interrupts not issued

1: SOF interrupts issued

R/W(0)

3.2.8

*3)

12 DVST

Device state transition interrupt status

0: Device state transition interrupts not issued

1: Device state transition interrupts issued

R/W(0)

3.2.6

*3)

11 CTRT

Control transfer stage transition interrupt

status

0: Control transfer stage transition interrupts

not issued

1: Control transfer stage transition interrupts

issued

R/W(0)

3.2.7

*3)

10 BEMP

Buffer Empty interrupt status

0: BEMP interrupts not issued

1: BEMP interrupts issued

3.2.5

*1)

NRDY

Buffer Not Ready interrupt status

0: NRDY interrupts not issued

1: NRDY interrupts issued

3.2.4

*1)

BRDY

Buffer Ready interrupt status

0: BRDY interrupts not issued

1: BRDY interrupts issued

3.2.3

*1)

VBSTS

VBUS input status

0: VBUS pin is “L” level

1: VBUS pin is “H” level

3.2.9

*2)

6-4 DVSQ

Device state

000: Powered state

001: Default state

010: Address state

011: Configured state

1xx: Suspended state

3.2.6

VALID

Setup packet reception

0: Not detected

1: Setup packet reception

R/W(0)

3.2.7

2-0 CTSQ

Control transfer stage

000: Idle or setup stage

001: Control read data stage

010: Control read status stage

011: Control write data stage

100: Control write status stage

101: Control write (NoData) status stage

110: Control transfer sequence error

111: Reserved

3.2.7

<<Note>>

*1) The BEMP, BRDY and NRDY bits are cleared when all of the factors for each pipe on correcponding registers

have been eliminated, i.e. BEMPSTS, BRDYSTS and NRDYSTS.

*2) The VBUS input status based on the VBSTS bit requires that chattering be eliminated using software.

*3) If multiple factors are being generated among the VBINT, RESM, SOFR, DVST, and CTRT bits, an access cycle

of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously.

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