M66596FP datasheet(25/131 Pages) RENESAS

25 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 25 of 127

2.5.1

Output pins drive current control

The output pins drive capability should be set using the LDRV bit of the PINCFG register, to match the VIF

power supply.

The output pins are the SD7-0, D15-0, INT_N, DREQx_N, DENDx_N, and SOF_N pins.

2.5.2

FIFO port access Endian

Table 2.7 and Table 2.8 show the byte Endian operation of the controller. (The controller uses Little Endian.) When

the CPU of user-system is Big-endian, software should be set the BIGEND bit to “1” of the PINCFG

Table 2.7 Endian operation when using 16-bit access

BIGEND

b15 – b8

b7 – b0

Odd-numbered addresses

Even-numbered addresses

Odd-numbered addresses

Table 2.8 Endian operation when using 8-bit access

BIGEND

b15 – b8

b7 – b0

Writing: invalid

Reading: invalid

Writing: valid

Reading: valid

Writing: valid

Reading: valid

Writing: invalid

Reading: invalid

2.5.3

DMA signal control

When transferring data using the DMA interface, the DMA operations (assertion and negation of the DREQx_N and

DENDx_N

signals, and the DMA transfer mode) should be specified to match the user system, using the BURST

PKTM

, DENDE, and OBUS bits of the DMAxCFG register. The DMA signals are valid for the selected pipe(s) as

long as DMA transfers are enabled using the DREQE bit of the DxFIFOSEL register, which will be explained

later. The DREQx_N pin is asserted when the buffer memory of the pipe is in the Buffer Ready (BRDY) state.

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