M66596FP datasheet(68/131 Pages) RENESAS

68 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 68 of 127

3.2.6

Device state transition interrupt

Figure 3.16 shows a diagram of the controller device state transitions. In the Peripheral mode, the controller

controls device states and generates device state transition interrupts. However, recovery from the suspended state

(Resume signal detection) is detected by means of the Resume interrupt. The device state transition interrupt can be

set when interrupts are enabled or disabled individually, using the INTENB0 register. Also, the device state that

underwent a transition can be confirmed using the DVSQ bit of the INTSTS0 register.

When making a transition to the default state, the device state transition interrupt is generated after the reset

handshake protocol has been completed.

Powered

State

(DVSQ="000")

Suspended state detection

(When SUSP=”1”, DVST is set to “1”)

Resume (RESM is set to “1”)

USB bus reset detection

(When URST=”1”, DVST is set to “1”)

SetAddress execution

(Address=0)

(When URST=”1”,

DVST is set to “1”)

Default

State

(DVSQ="001")

Address

State

(DVSQ="010")

Configured

State

(DVSQ="011")

Suspended

State

(DVSQ="100")

Suspended

State

(DVSQ="101")

Suspended

State

(DVSQ="110")

Suspended

State

(DVSQ="111")

Suspended state detection

(When SUSP=”1”, DVST is set to “1”)

Resume (RESM is set to “1”)

SetAddress execution

(When SADR=”1”, DVST is set to “1”)

Suspended state detection

(When SUSP=”1”, DVST is set to “1”)

SetConfiguration

execution

(ConfigurationValue=0)

(When SADR=”1”, DVST

is set to “1”)

SetConfiguration execution

(ConfigurationValue?0)

(When SCFG=”1”, DVST is set to “1”)

Note: The URST, SADR, SCFG and SUSP bits in parentheses are the bits that are permitted when the controller

sets the DVST bit to “1” when the pertinent stage transition is generated (interrupt enable register 0

[INTENB0]). Stage transitions are carried out even if setting the DVST bit to “1” is inhibited by these bits.

USB bus reset detection

(When URST=”1”,

DVST is set to “1”)

Resume (RESM is set to “1”)

Suspended state detection

(When SUSP=”1”, DVST is set to “1”)

Resume (RESM is set to “1”)

Figure 3.16 Device state transitions

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