M66596FP datasheet(48/131 Pages) RENESAS

48 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 48 of 127

PIPE1 control register [PIPE1CTR]

<Address: 70H>

PIPE2 control register [PIPE2CTR]

<Address: 72H>

PIPE3 control register [PIPE3CTR]

<Address: 74H>

PIPE4 control register [PIPE4CTR]

<Address: 76H>

PIPE5 control register [PIPE5CTR]

<Address: 78H>

PIPE6 control register [PIPE6CTR]

<Address: 7AH>

PIPE7 control register [PIPE7CTR]

<Address: 7CH>

BSTS INBUFM

ACLRM SQCLR SQSET SQMON

PID

Bit

Name

Function

S/W

H/W

Note

BSTS

Buffer Status

0: Buffer access is disabled.

1: Buffer access is enabled.

3.4.1.1

*12)

INBUFM

Sending buffer status monitor

0: No data which can be transmitted in a buffer

1: The data which can be transmitted is in a buffer

memory.

3.4.1.1

*13),

*14)

13-10 Nothing is placed here. These should be fixed at “0”.

ACLRM

Auto Buffer Clear mode

0: Disabled

1: Enabled (all buffers are initialized)

R(0)/

W(1)

R/W(0) 3.4.1.4

*15)

SQCLR

Toggle Bit Clear

0: Invalid

1: Specifies DATA0

R(0)/

W(1)

3.3*16),

*17)

SQSET

Toggle Bit Set

0: Invalid

1: Specifies DATA1

R(0)/

W(1)

3.3

*16),

*17)

SQMON

Toggle Bit Confirm

0: DATA0

1: DATA1

3.3

5-2 Nothing is placed here. These should be fixed at “0”.

1-0 PID

Response PID

00: NAK response

01: BUF response (in keeping with the buffer state)

10: STALL response

11: STALL response

R/W

3.3

*18)

<<Notes>>

*12) The direction of buffer access, writing or reading, is depend on setting of the DIR bit of the PIPECFG register.

*13) The INBUFM bit is valid when softwware sets the DIR bit to Sending-direction.

*14) The INBUFM bit is valid for PIPE1-5.

*15) Software should not set “ACLRM=1” for the PIPE whith selected by the CURPIPE bit of the CFIFOSEL,

DxFIFOSEL

*16) If the SQCLR bits and the SQSET bits of the DCPCTR register and the PIPExCTR registers are being used to

change the data PID sequence toggle bit for several pipes in succession, an access cycle of at least 200 ns is

required.

*17) The SQCLR bit and SQSET bit should not both be set to “1” at the same time. Before operating either bit,

“PID=NAK” should be set.

*18) The operation is as follows, when setting up PID=BUF.

Host mode and the transmitting direction (OUT).

A transaction is issued when there is transmitting data in a buffer.

A transaction is not issued when there is no transmitting data in a buffer.

Host mode and the receiving direction (IN).

A transaction is issued when there is no receiving data in a buffer.

A transaction is not issued when there is receiving data in a buffer.

Peripheral mode and the transmitting direction (OUT).

A ACK response and receiving a data , when there is no receiving data in a buffer.

A NAK response is carried out to a token, when there is a receiving data in a buffer.

Peripheral mode and the receiving direction (IN).

A Data is transmitted to a IN token.

A NAK response is carried out to a IN token, when there is a transmitting data in a buffer.

And at the time of occurring of a transmission error etc., PID bits are set up by the controller and transmission

is ended.

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