M66596FP datasheet(98/131 Pages) RENESAS

98 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 98 of 127

3.11 Communication schedule

3.11.1 The generation conditions of a transaction

In the Host mode, This controller generates a transaction according to the following conditions after supply of an

internal clock, and a setup of "UACT=1."

Table 3.27 The generation conditions of a transaction

Generation conditions

Transaction

DIR

PID

IITV*2)

Status of buffer

SUREQ

Setup

Set 1

BUF

Invalid

There is a

receiving area

The data stage of control

transmission, status

stage, bulk transfer

OUT

BUF

Invalid

There is a

sending data

BUF

Effective

There is a

receiving area

Interrupt transfer

OUT

BUF

Effective

There is a

sending data

Isochronous transfer

BUF

Effective

*3)

OUT

BUF

Effective

*4)

*1) It is shown that slashes are conditions which are unrelated to generation of a token.

*2) The Effective means being generated only with the transmission frame by the interval counter. It is shown that

the Invalid is generated regardless of an interval counter.

*3) The controller generates a transaction regardless of a receiving area. However, receiving data is canceled when

there is no receiving area.

*4) The controller generates a transaction regardless of a sending data. However, when there is no transmitting

data, Zero-Length Packet is transmitted.

3.11.2 Communication schedule

This chapter explains the scheduling of transmission in the frame of this controller. After transmitting SOF ,

this controller transmits packets as follows.

(1) Execution of periodic transmission

The controller executes transactions, if it searches in order of PIPE1 ->PIPE2 ->PIPE6 ->PIPE7 and there is

a pipe in which the transaction of isochronous transfer or interrupt transfer is possible.

(2) Execute setup transaction of control transfer

DCP is checked, and if the setup transaction is possible, it will transmit.

(3) Execute bulk transfer, data stage and status stage of control transfer,

The controller searches PIPEs in following order. And a transaction will be executed if there is PIPE which

can execute the transaction of bulk, a control transmission data stage, and a control transmission status

stage.

The order of search : DCP -> PIPE1 -> PIPE2 -> PIPE3 -> PIPE4 -> PIPE5

When a transaction is executed, regardless of the response from Peripheral, it moves to the next PIPE.

Moreover, (3) will be repeated if there is time to transmit in a frame.

3.11.3 USB Communication enable

By setting the UACT bit of a DVSTCTR register as "1", transmission of SOF or uSOF is started and execution

of a transaction is enabled.

If a UACT bit is set as "0", transmission of SOF or uSOF will be stopped and it will be suspended. When

setting a UACT bit as 1->0, a controller stops sending packets, after it transmits next SOF or next uSOF.

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