M66596FP datasheet(65/131 Pages) RENESAS

65 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 65 of 127

If a Zero-Length packet has been received, the pertinent bit of the BRDYSTS register goes to “1”, but the data of

the pertinent packet cannot be read. The buffer should be cleared (“BCLR=1”) after clearing the BRDYSTS register.

With PIPE1-PIPE7, if DMA transfer is being carried out in the reading direction, interrupts can be generated in

transfer units, by setting the BFRE bit of the PIPECFG register.

Zero-Length packet reception

Data packet reception using BFRE = 0 (Short Packet / Transaction Counter / Buffer Full)

Token Packet

Zero-Length Packet /

Short Data Packet /

Data Packet (Full)

(Transaction Count)

USB bus

ACK Handshake

Data packet reception using BFRE = 1 (Short Packet / Transaction Counter)

Token Packet

USB bus

ACK Handshake

Buffer Read

Packet transmission

Token Packet

Data Packet

USB bus

ACK Handshake

Buffer Write

Short Data Packet /

Data Packet

(Transaction Count)

BRDY interrupt

A BRDY interrupt is generated because

reading from the buffer is enabled.

A BRDY interrupt is generated because

writing to the buffer is enabled.

A BRDY interrupt is generated

because the transfer has ended.

Figure 3.13 Timing at which BRDY interrupts are generated

The conditions on which this controller clears the BRDY bit of INTSTS0 register change with setting values of the

BRDYM

bit of INTENB1 register. BRDY bit clear conditions are shown in Table 3.10.

Table 3.10 Conditions for elimination of the BRDY bit

BRDYM

Conditions for elimination of the BRDY bit

When software clears all enabled bits of the BRDYSTS register, the controller clears the BRDY

bit.

When the controller clears all BSTS bits which corresponding to BRDY interrupt enebled pipe,

the controller clears the BRDY bit.

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