M66596FP datasheet(18/131 Pages) RENESAS

18 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 18 of 127

2.3 System control

System configuration control register [SYSCFG]

XTAL

XCKE

RCKE

PLLC

SCKE

ATCKM

HSE

DCFM DMRPD DPRPU

FSRPC PCUT

USBE

Bit

Name

Function

S/W

H/W

Note

15-14 XTAL

Clock selection

00: 12 MHz input

01: 24 MHz input

10: 48 MHz input

11: Reserved

R/W

3.1.6

XCKE

Oscillation buffer enabled

0: Oscillation buffer operation disabled

1: Oscillation buffer operation enabled

R/W

(1)

3.1.6

*2)

RCKE

Reference clock enabled

0: Reference clock supply stopped

1: Reference clock supply enabled

R/W

3.1.6

PLLC

PLL operation enabled

0: PLL operation disabled

1: PLL operation enabled

R/W

3.1.6

SCKE

Internal clock enabled

0: Internal clock supply stopped

1: Internal clock supply enabled

R/W

3.1.6

Nothing is placed here. It should be fixed at “0”.

ATCKM

Auto clock supply function enabled

The clock is supplied from the low-power sleep

state or clock stop state.

0: Auto clock supply function disabled

1: Auto clock supply function enabled

R/W

3.1.7

HSE

Hi-Speed operation enabled

This enables Hi-Speed operation.

0: Hi-Speed operation disabled (Full-Speed)

1: Hi-Speed operation enabled (detected by

controller)

R/W

2.3.1

3.1.4

*1)

DCFM

0: Peripheral Controller

1: Host Controller

R/W

2.3.1

*1)

DMRPD

D+,D- line resistance control

R/W

2.3.4

DPRPU

D+,D- line resistance control

For detailed information, refer to Chapter 2.3.4

R/W

2.3.4

Nothing is placed here. These should be fixed at “0”.

FSRPC

Full-Speed receiver enable

0: Full-Speed receiver is controled by H/W

1: Full-Speed receiver enabled by S/W

R/W

2.3.3

PCUT

Low-power sleep state enabled

0: Normal operation state

1: Low-power sleep state

R/W (1) R/W

(0)

*1)

USBE

USB block operation enabled

0: USB block operation disabled (S/W Reset)

1: USB block operation enabled

R/W

2.3.2

3.1.4

<< Notes >>

*1) The Hi-Speed operation enabled (HSE) bit and Device Controller function (DCFM) should be set before the

internal clock is supplied and .setup DPRPU and DPRPD bit.

*2) When the system returns from the low-power sleep state to the normal operation state, the controller sets

“XCKE = 1”.

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