M66596FP datasheet(24/131 Pages) RENESAS

24 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 24 of 127

The DMA0CFG register controls the input/output pins used for the DMA0 interface and the D0FIFO port, and the

DMA1CFG

DMA0 pin configuration register [DMA0CFG]

<Address: 0CH>

DMA1 pin configuration register [DMA1CFG]

<Address: 0EH>

DREQA BURST

DACKA

DFORM

DENDA PKTM DENDE

OBUS

Bit

Name

Function

S/W

H/W

Note

15 Nothing is placed here. This should be fixed at “0”.

14 DREQA

DREQx_N signal polarity selection

This specifies the active state for the DREQx_N

pin.

0: Low active

1: High active

R/W

13 BURST

Burst mode

0: Cycle steal transfer

1: Burst transfer

R/W

2.5.3

*3)

12-11 Nothing is placed here. These should be fixed at “0”.

10 DACKA

DACKx_N signal polarity selection

This specifies the active state for the DACKx_N

pin.

0: Low active

1: High active

R/W

9-7 DFORM

DMA transfer signal selection

011:

Only the DACKx_N signal is used (CPU

bus).

000:

The Address signal + the RD_N/WRx_

signals are used (CPU bus).

010:

The DACKx_N + the RD_N/WRx_N

signals are used (CPU bus).

100:

The DACKx_N signal is used (split bus).

110:

The DACK0_N + the DSTB0_N signal

are used (split bus).

001, 101, 111: Reserved

R/W

3.4.3

*3)

DENDA

DEND0_N signal polarity selection

This specifies the active state of the DENDx_N

pin.

0: Low active

1: High active

R/W

PKTM

Packet mode

0: The DENDx_N signal is asserted in transfer

units.

1: The DENDx_N signal is asserted each time

an amount of data corresponding to the buffer

size is transferred.

R/W

2.5.3

3.4.3.4

*2)

DENDE

DENDx_N signal enabled

0: The DENDx_N signal is disabled

(Hi-Z output).

1: The DENDx_N signal is enabled.

R/W

2.5.3

3.4.3.4

Nothing is placed here. It should be fixed at “0”.

OBUS

OBUS operation

disabled

0: The OBUS mode is enabled.

1: The OBUS mode is disabled.

R/W

3.5

1-0 Nothing is placed here. These should be fixed at "0”.

<<Notes>>

*2) The PKTM bit is valid only when the data receiving direction (reading from the buffer memory) is set. If the

DxFIFO port is being used in the data writing direction, “PKTM=0” should be set.

*3) The “DFORM=110” setting is valid only when the DMA channel 0 is set.

Also, the following should not be set: "DFORM=001”,"DFORM=101” and"DFORM=111”.

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