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RIVA128 датащи(PDF) 48 Page - STMicroelectronics |
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RIVA128 датащи(HTML) 48 Page - STMicroelectronics |
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48 / 77 page ![]() 128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 48/77 Table 14. ROM interface timing parameters NOTE 1TMCLK is the period of the internal memory clock. 2 This parameter is programmable in the range 0 - 3 MCLK cycles 3 This parameter is programmable in the range 0 - 15 MCLK cycles Symbol Parameter Min. Max. Unit Notes tBRCS ROMCS# active pulse width 20TMCLK-5 ns tBRCA ROMCS# precharge time TMCLK-5 ns tBRV Read valid to ROMCS# active TMCLK-5 ns tBRH Read hold from ROMCS# inactive TMCLK-5 ns tBAS Address setup to ROMCS# active TMCLK-5 ns tBAH Address hold from ROMCS# inactive TMCLK-5 ns tBOS OE# low from ROMCS# active ns 2 tBOH OE# low to ROMCS# inactive ns 3 tBWS WE# low from ROMCS# active ns 2 tBWL WE# low time ns 3 tBDBZ Data bus high-z to ROMCS# active TMCLK-5 ns tBDS Data setup to ROMCS# inactive 10 ns tBDH Data hold from ROMCS# inactive 0 ns tBDZ Data high-z from ROMCS# inactive TMCLK-5 ns tBWDH Write data hold from ROMCS# inactive 0.5TMCLK-5 ns tBWDS ROM write data setup to ROMCS# active TMCLK-5 ns |
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