RIVA128 datasheet(45/77 Pages) STMICROELECTRONICS

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128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

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8.4

656 MASTER MODE

Table 11 shows the Video Port pin definition when

the RIVA 128 is configured in ITU-R-656 Master

Mode. Before entering this mode, RIVA 128 dis-

ables all Video Port devices so that the bus is tri-

stated. The RIVA 128 will then enable the video

656 master device through the serial bus. In this

mode, the video device outputs the video data

continuously at the PIXCLK rate.

Table 11.

656 master mode pin definition

The 656 Master Mode assumes that VID[7:0] and

PIXCLK can be tri-stated when the slave is inac-

tive. If a slave cannot tri-state all its signals, an ex-

ternal tri-state buffer is needed.

Video data capture

Video Port pixel data is clocked into the port by the

external pixel clock and then passed to the RIVA

128's video capture FIFO.

Pixel data capture is controlled by the ITU-R-656

codes embedded in the data stream; each active

line beginning with SAV (start active video) and

ending with EAV (end active video).

In normal operation, when SAV = x00, capture of

video data begins, and when EAV = xx1, capture

of video data ends for that line. When VBI (Vertical

Blanking Interval) capture is active, these rules are

modified.

656 master mode timing specification

Figure 54.

656 Master Mode timing diagram

Table 12.

ITU-R-656 Master Mode timing parameters

NOTE

VACTIVE indicates that valid pixel data is being transmitted across the video port.

Table 13.

YUV (YCbCr) byte ordering

Normal Mode

656 Master Mode

MPCLK

PIXCLK

MPAD[7:0]

VID[7:0]

MPFRAME#

Not used

MPDTACK#

Not used

MPSTOP#

Not used

Symbol

Parameter

Min.

Max.

Unit

Notes

VID[7:0] hold from PIXCLK high

VID[7:0] setup to PIXCLK high

PIXCLK cycle time

1st byte

2nd byte

3rd byte

4th byte

5th (next

dword)

6th byte

7th byte

U[7:0]

Y0[7:0]

V[7:0]

Y1[7:0]

U[7:0]

Y0[7:0]

V[7:0]

Cb[7:0]

Y0[7:0]

Cr[7:0]

Y1[7:0]

Cb[7:0]

Y0[7:0]

Cr[7:0]

PIXCLK

VID[7:0]

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