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RIVA128 датащи(PDF) 22 Page - STMicroelectronics

номер детали RIVA128
подробное описание детали  RIVA 128™ 128-BIT 3D MULTIMEDIA ACCELERATOR
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производитель  STMICROELECTRONICS [STMicroelectronics]
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5.2
PCI TIMING SPECIFICATION
The timing specification of the PCI interface takes the form of generic setup, hold and delay times of tran-
sitions to and from the rising edge of PCICLK as shown in Figure 11.
Figure 11.
PCI timing parameters
Table 4.
PCI timing parameters
NOTE
1
PCIREQ# and PCIGNT# are point to point signals and have different valid delay and input setup times than bussed sig-
nals. All other signals are bussed.
Symbol
Parameter
Min.
Max.
Unit
Notes
tVAL
PCICLK to signal valid delay (bussed signals)
2
11
ns
1
tVAL(PTP)
PCICLK to signal valid delay (point to point)
2
12
ns
1
tON
Float to active delay
2
ns
tOFF
Active to float delay
28
ns
tSU
Input set up time to PCICLK (bussed signals)
7
ns
1
tSU(PTP)
Input set up time to PCICLK (PCIGNT#)10
ns
1
tSU(PTP)
Input set up time to PCICLK (PCIREQ#)12
ns
tH
Input hold time from PCICLK
0ns
tVAL
tON
tOFF
tSU
tH
PCICLK
Output delay
Tri-state output
Input
PCICLK
Output timing parameters
Input timing parameters



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