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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RIVA128 датащи(PDF) 33 Page - STMicroelectronics |
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RIVA128 датащи(HTML) 33 Page - STMicroelectronics |
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33 / 77 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 33/77 Figure 28. SGRAM read to write, read latency of three Table 7. SGRAM I/O timing parameters Figure 29. SGRAM random write cycles within a page NOTE 1 Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active (low). Figure 30. SGRAM write to read cycle NOTE 1 A read latency of 2 is shown for illustration Symbol Parameter Min. Max. Unit Notes tHZ Data out high impedance time 4 10 ns tDS Write data setup time 4 ns tHZ tDS read nop nop read data n nop write bank, col n write data b bank, col b FBCLKx TDDQM Command FBA[9:0] FBD[63:0] write write write write data n data a data x data m bank, col n bank, col a bank, col x bank, col m FBCLKx Command FBA[9:0] FBD[63:0] write nop read nop nop nop bank, col n bank, col b write data n write data n read data b FBCLKx Command FBA[9:0] FBD[63:0] |
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