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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RIVA128 датащи(PDF) 68 Page - STMicroelectronics |
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RIVA128 датащи(HTML) 68 Page - STMicroelectronics |
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68 / 77 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 68/77 Byte offsets 0x13 - 0x10 Base Memory Address Register (0x13 - 0x10) 0x13 0x12 0x11 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits Function R W I 31:24 The BASE_ADDRESS bits contain the most significant bits of the base address of the device. This indicates that the RIVA 128 requires a 16MByte block of contiguous memory beginning on a 16MByte boundary. This memory range contains memory-mapped registers and FIFOs and should not be set as part of a PentiumPro™’s write combining range. R W 0 23:4 The BASE_RESERVED bits form the least significant bits of the base address and are hardwired to 0. R - 0 3 The PREFETCHABLE bit indicates that there are no side effects on reads, that the device returns all bytes on reads regardless of the byte enables, and that host bridges can merge processor writes into this range without causing errors. R - 1 2:1 The ADDRESS_TYPE bits contain the type (width) of the Base Address. 0=32-bit R - 0 0 The SPACE_TYPE bit indicates whether the register maps into Memory or I/O space. 0=Memory space R - 0 |
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