RIVA128 datasheet(30/77 Pages) STMICROELECTRONICS

30 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

30/77

Table 5.

Truth table of supported SGRAM commands

NOTES

FBCKE is high and DSF is low for all supported commands.

Activates or deactivates FBD[127:0] during writes (zero clock delay) and reads (two-clock delay).

6.1

SGRAM INITIALIZATION

SGRAMs must be powered-up and initialized in a predefined manner. The first SGRAM command is reg-

istered on the first clock edge following PCIRST# inactive.

All internal SGRAM banks are precharged to bring the device(s) into the “all bank idle” state. The SGRAM

mode registers are then programmed and loaded to bring them into a defined state before performing any

operational command.

6.2

SGRAM MODE REGISTER

The Mode register defines the mode of operation of the SGRAM. This includes burst length, burst type,

read latency and SGRAM operating mode. The Mode register is programmed via the Load Mode register

and retains its state until reprogrammed or power-down.

Mode register bits M[2:0] specify the burst length; for the RIVA 128 SGRAM interface these bits are set to

zero, selecting a burst length of one. In this case FBA[7:0] select the unique column to be accessed and

Mode register bit M[3] is ignored. Mode register bits M[6:4] specify the read latency; for the RIVA 128

SGRAM interface these bits are set to either 2 or 3, selecting a burst length of 2 or 3 respectively.

Command1

FBCSx

FBRAS# FBCAS# FBWE#

FBDQM

FBA[9:0]

FBD[63:0] Notes

Command inhibit (NOP)

xxxx

No operation (NOP)

Active (select bank and

activate row)

FBA[9]=bank

FBA[8:0]=row

Read (select bank and

column and start read

burst)

FBA[9]=bank

FBA[8]=0

FBA[7:0]=row

Write (select bank and

column and start write

burst)

FBA[9]=bank

FBA[8]=0

FBA[7:0]=row

valid data

Precharge (deactivate

row in both banks)

FBA[8]=1

Load mode register

LLL

FBA[8:0] =

opcode

Write enable/output

enable

----

active

Write inhibit/output

High-Z

----

high-Z

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