RIVA128 datasheet(40/77 Pages) STMICROELECTRONICS

40 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

40/77

8.2

BI-DIRECTIONAL MEDIA PORT POLLING

COMMANDS USING MPC

The Media Port transfers data using a Polling Pro-

tocol. The Media Port is enabled on the RIVA 128

by the host system software. The first cycle after

being enabled is a Poll Cycle. The MPC ASIC

must respond to every poll cycle with valid data

during DTACK active. If no transactions are need-

ed, it responds with 00h. The Media Port will con-

tinue to Poll until a transaction is requested, or un-

til there is a Host CPU access to an external reg-

ister.

Polling Cycle

Media Port initiates a Polling Cycle whenever

there is no pending transaction. This gives the

MPC ASIC a mechanism to initiate a transaction.

The valid Polling commands are listed in the Poll-

ing Command table. The priority for the polling re-

quests should be to give the Display Data FIFO

highest priority.

CPU Register Write

Initiated by the Host system software.

CPU Register Read Issue

Initiated by the Host system software. The read

differs from the write in the fact that it must be done

in two separate transfers. The Read Issue is just

the initiation of the read cycle. The Media Port

transfers the address of the register to be read

during this cycle. After completion of the Read Is-

sue cycle the media port goes back to polling for

the next transaction. When it receives a Read

Data ready command, it will start the next cycle in

the read.

CPU Register Read Receive

Initiated by the MPC ASIC when it has read data

ready to be transferred to the media port. The

MPC ASIC waits for the next polling cycle and re-

turns a Read Data Ready status. The media port

will transfer the read data on the next Read Re-

ceive Cycle. The PCI bus will be held off and retry

until the register read is complete.

Video Compressed Data DMA Write

Initiated by the MPC ASIC with the appropriate

Polling Command. The media port manages the

Video Compressed data buffer in system memory.

Each request for data will return 32 bytes in a sin-

gle burst.

Display Data DMA Read

Initiated by the MPC ASIC with the polling com-

mand. The MPC ASIC initiates this transfer when

it wishes to transfer video data in ITU-R-656 for-

mat.

Table 9.

Media Port Transactions

Table 10.

Polling Cycle Commands

A0 Cycle

Transaction

Description

11xx0000

Poll_Cycle

Polling Cycle

00xx----

CPUWrite

CPU Register Write

01xx1111

CPURead_Issue

CPU Register Read Issue

11xx1111

CPURead_Receive

CPU Register Read Receive

01xx0001

VCD_DMA_Write

Video Compressed Data DMA Write

11xx1000

Display_Data_Read

Display Data DMA Read

BIT

Data

Description

000xxxx1

NV_PME_VMI_POLL_UNCD

Request DMA Read of Display Data

000xxx1x

NV_PME_VMI_POLL_VIDCD

Request DMA Write of Video Compressed Data

000x1xxx

NV_PME_VMI_POLL_INT

Request for Interrupt

0001xxxx

NV_PME_VMI_POLL_CPURDREC

Respond to Read Issue - Read Data Ready

00000000

NULL

No Transactions requested

RIVA128 датащи(PDF) 40 Page - STMicroelectronics

RIVA128 датащи(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL