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RIVA128 датащи(PDF) 32 Page - STMicroelectronics |
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RIVA128 датащи(HTML) 32 Page - STMicroelectronics |
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32 / 77 page ![]() 128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 32/77 Figure 26. SGRAM random read accesses within a page, read latency of two1 NOTE 1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. DQMs are all active (LOW). Figure 27. SGRAM random read accesses within a page, read latency of three1 NOTE 1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. FBDQM is all active (LOW). tCL CLK low time 3.5 4.5 - - ns tAS Address setup time 3 4 - ns tAH Address hold time 1 1 - ns tDS Write data setup time 3 4 - ns tDH Write data hold time 1 1 - ns tOH Read data hold time 3 3 - ns tAC Read data access time 9 9 - ns tLZ Data out low impedance time 0 0 - ns Symbol Parameter Min. Max. Unit Notes -10 -12 -10 -12 read read read data n data a read nop nop bank, col n bank, col a bank, col x bank, col m data x data m FBCLKx Command FBA[9:0] FBD[63:0] read read read data n read nop nop bank, col n bank, col a bank, col x bank, col m data a data x data m nop FBCLKx Command FBA[9:0] FBD[63:0] |
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