TAS2781RYYR datasheet(75/90 Pages) TI2

75 / 90 page

11 Power Supply Recommendations

The power sequence between the supply rails can be applied in any order as long as SDZ pin is held low.

Once all supplies are stable the SDZ pin can be set high to initialize the part. After a hardware or software reset

additional commands to the device should be delayed for at least 1 ms to allow the OTP memory to load (see

section Section 10).

When PVDDL is internally generated (see Section 11.1) it is recommended that the device enters Software

Shutdown mode before entering Hardware Shutdown mode. This ensures that PVDDL pin is discharged using

the internal 5 kOhms pull down resistor (not present in Hardware Shutdown mode).

11.1 Power Supply Modes

The TAS2781 can operate with both PVDDL and PVDDH as supplies or with only PVDDH or PVDDL as supply.

The table below shows different power supply modes of operation depending on the user need.

Table 11-1. Device Configuration and Power Supply Modes

Supply Power Mode

Output

Switching

Mode

Supply

Condition

PVDDL

Mode

Device

Configurations

Use Case and Device Functionality

PWR_MODE0

High Power on

PVDDH

PVDDH>PVDDL

External

PVDDL_MODE=0

CDS_MODE[1:0]=10

PVDDH is the only supply used to

deliver output power.

PWR_MODE1

Y Bridge - High

Power on

PVDDL

PVDDH

External

PVDDL_MODE=0

CDS_MODE[1:0]=00

PVDDL is used to deliver output

power based on level and headroom

configured. When audio signal crosses

a programmed threshold Class-D output

is switched over PVDDH.

PWR_MODE2

Y Bridge - Low

Power on

PVDDL

PVDDH

Internal

PVDDL_MODE=1

CDS_MODE[1:0]=11

PVDDH is the only supply. PVDDL is

delivered by an internal LDO and used

to supply at signals close to idle channel

levels. When audio signal levels crosses

-100dBFS (default), Class-D output

switches to PVDDH.

PWR_MODE3

PVDDL

External

PVDDL_MODE=0

CDS_MODE[1:0]=01

The device can be forced to work out

of a low power rail mode of operation.

For example this can be used for a low

power ultrasonic chirp when audio is not

played.

When PVDDL is external (PWR_MODE0, PWR_MODE1), if PVDDH falls below (PVDDL + 2.5 V) level, the

Y-bridge will stop switching between supplies and will remain on the PVDDH supply.

In PWR_MODE2 user needs to ensure that PVDDH supply level is at least 2.5 V above the PVDDL voltage

generated internally in order to take advantage of Y bridge mode of operation. To enable voltage protection the

under voltage threshold of PVDDH supply should be set above 7.3 V by using register bits PVDD_UVLO[5:0].

This will ensure that, with an internally generated PVDDL of 4.8 V, PVDDH supply is at least 2.5 V higher than

PVDDL.

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TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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