TAS2781RYYR datasheet(23/90 Pages) TI2

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Y-bridge mode the device will use only the selected supply for Class-D output even if clipping would otherwise

occur. The device can operate using only PVDDH to supply Class-D output. In this configuration the PVDDL can

be provided from external supply (register bit PVDDL_MODE=0) or generated by an internal LDO (register bit

PVDDL_MODE[7]=1). In this case CDS_MODE[7:6] bits should be set to 2'b10. The TAS2781 Y-Bridge with low

power on PVDDL can be used to switch to the PVDDL rail only at very low power when close to idle. This will

reduce the Class-D output swing when near idle and limit the current requirements of the PVDDL supply. Set the

CDS_MODE[7:6] register to 2'b11 for this mode.

See for details on programming the power mode of operation.

The change to the Class-D supply (PVDDL to PVDDH) determined by the has a delay with respect to input

signal crossing threshold and it can be programed using CDS_DLY[1:0] bits of register from .

When in Y-Bridge mode, if the PVDDH falls below (PVDDL + 2.5 V) level, the Y-Bridge will stop switching

between supplies and will remain on the PVDDH supply.

8.4.2.7 Low Voltage Signaling (LVS)

The TAS2781 is a mechanism used in connection with the Y Bridge confiuration of the output stage of Class-D.

It is based on monitoring the absolute value of the audio stream and selecting the proper supply, PVDDH or

PVDDL.

When the signal is initially above the programmed LVS threshold the Class-D is supplied by PVDDH rail. If the

signal level drops below this threshold for longer than the hysteresis time defined by LVS_HYS[3:0] register bits,

the Class-D supply will switch to PVDDL. If the signal goes back to the initial level the Class-D supply will switch

back to PVDDH.

By default he LVS threshold is configured to be a value relative to the PVDDL voltage (LVS_DET = 1). Use the

LVS_RTH[3:0] register bits for setting the threshold (default = 0.7 V).

Setting bit LVS_DET bit to low forces the LVS threshold to a fixed value defined by the LVS_FTH[4:0] register

bits.

LVS threshold is refered relative to the output signal level and it is measured in dBFS.

In an use case when CDS_MODE[1:0]=11 (PWR_MODE2 from Section 11.1), the fixed LVS threshold can be set

using register bits LVS_TH_LOW[1:0].

8.4.2.8 Noise Gate Mode

The TAS2781 has a noise-gate feature that monitors the input signal and powers down the Class-D

when the signal goes below the set threshold set by NG_TH[1:0] bits for longer than the time set by

NG_HYST_TIMER[2:0] bits of register from . When the signal goes above the threshold the Class-D will re-

power in seven samples before the samples applied to the audio input interface reach the Class-D output.

The Noise Gate feature is enabled by setting NG_EN bit to high. Once enabled it is able to power up and down

the channel within the device processing delay requiring no additional external control. Volume ramping can be

also used during noise gate operations by setting NG_DVC_RP bit to low.

The noise gate can be configured with finer resolution at the expense of additional I2C writes. Use NGFR_EN

bit to enable this mode and register bits NGFR_LVL[23:0] from to set the fine resolution. The fine resolution

hysteresis is set using NGFR_HYST[18:3] register bits from and from .

8.4.2.9 Supply Tracking Limiter

The TAS2781 monitors PVDDH supply voltage and the audio signal to automatically decrease gain when the

audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time

through end of charge battery conditions. The limiter threshold can be configured to track PVDDH below a

programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold

reduction from PVDDH tracking.

The limiter is enabled by setting the LIM_EN bit register to high.

www.ti.com

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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