TAS2781RYYR datasheet(5/90 Pages) TI2

5 / 90 page

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)

±500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

AVDD

Supply voltage

1.65

1.8

1.95

IOVDD

Supply voltage

3.3

3.6

1.65

1.8

1.95

NC_V1P8V

Supply voltage for ICC Pin

1.65

1.8

1.95

PVDDH(2)

Supply voltage

(functional)(1)

Min operating free-air and Min operating

junction temperature of -20°C

Min operating free-air and Min operating

junction temperature of -40°C

Supply voltage

(performance)

Min operating free-air and Min operating

junction temperature of -20°C

4.5

Min operating free-air and Min operating

junction temperature of -40°C

4.5

PVDDL

Supply voltage (functional)(1)

2.7

5.5

Supply voltage (performance with Y-bridge disabled)

3.5

5.5

Supply voltage (performance with Y-bridge enabled)

2.7

5.5

RSPK

Speaker impedance

3.2

LSPK

Speaker inductance

µH

(1)

Device will remain functional but performance may degrade.

(2)

PVDDH supply voltage should be greater than PVDDL-0.7 V.

6.4 Thermal Information

THERMAL METRIC(1)

UNIT

HR_QFN

30 PINS

RθJA

Junction-to-ambient thermal resistance

44.2

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

22.4

°C/W

RθJB

Junction-to-board thermal resistance

12.3

°C/W

ψJT

Junction-to-top characterization parameter

0.6

°C/W

ψJB

Junction-to-board characterization parameter

12.1

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

TA = 25 °C, PVDDH = 18 V, PVDDL= 3.8 V, AVDD = 1.8 V, IOVDD =1.8 V, RL = 4Ω + 15µH, fin = 1 kHz, fs = 48 kHz, Gain =

21 dBV, SDZ = 1, NG_EN=0, EN_LLSR=0, PWR_MODE1, Measured filter free as in Section 7 (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT and OUTPUT

VIH

High-level digital input logic

voltage threshold

SBLK, FSYNC, SDIN, SCL_nSCS, SDA_SDI

0.7xIOVDD

VIL

Low-level digital input logic

voltage threshold

SBLK, FSYNC, SDIN, SCL_nSCS, SDA_SDI

0.3 x

IOVDD

VIH(SDZ)

High-level digital input logic

voltage threshold

SDZ

0.7xAVDD

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TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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