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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TAS2781RYYR датащи(PDF) 3 Page - Texas Instruments |
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TAS2781RYYR датащи(HTML) 3 Page - Texas Instruments |
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3 / 90 page  5 Pin Configuration and Functions Figure 5-1. Package 30-Pin HR-QFN Bottom View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. ADDR 23 I Address detect pin. Resistor value at this pin selects the I2C address. See Section 8.3.2. AVDD 24 P Analog power input. Connect to 1.8 V supply and decouple to GND with capacitor. BSTN 30 P Class-D negative bootstrap. Connect a capacitor between BSTN and OUTN. BSTP 4 P Class-D positive bootstrap. Connect a capacitor between BSTP and OUTP. DGND 25 P Device substrate ground. Connect to PCB ground plane. Avoid any common routing inductance between this pin and GND pin. DREG 10 P Digital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to external load. FSYNC 14 I Frame Synchronization Clock. GND 7 P Analog ground. Connect to PCB ground plane. ICC 6 IO Inter-chip communication pin used to transmit gain alignment. Connect to GND if not used. IOVDD 20 P Digital IO Supply. Connect to 1.8 V or 3.3 V IO supply and decouple with a capacitor to GND. IRQZ 21 O Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pull up is not used. MODE 26 I External configuration defines the mode of operation. NC 16 - Tied to GND. NC_SCLK 9 I I2C Mode: NC = Tied to GND, SPI Mode: Clock pin. NC_SDO 8 O I2C Mode: NC = Tied to GND, SPI Mode: Serial data output pin. www.ti.com TAS2781 SLOSE86B – JULY 2022 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TAS2781 |
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