TAS2781RYYR datasheet(27/90 Pages) TI2

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the PFFB_EN register bit (if an external filter that violates the amplifier loop stability is implemented). When

PFFB is disabled, the feedback will be internally routed from the OUTN and OUTP pins of the device.

In the PFFB mode of operation the following conditions have to be met: f0 > 10 MHz and f0/Q > 2.5 MHz (f0 and

Q are the cutoff frequency and the quality factor of the external filter).

8.4.6 Thermal Foldback

The TAS2781 monitors the die temperature and can automatically limit the audio signal when the die

temperature reaches a set threshold. It is recommended to use the thermal fold-back registers to configure

this protection mechanism as the internal DSP will perform the necessary calculation for each register.

Thermal fold-back can be disabled using TFB_EN bit . If the die temperature reaches the value set by

TF_TMP_TH[31:0] bits of register from this feature will begin to attenuate the audio signal to prevent the device

from shutting down due to over-temperature. It will attenuate the audio signal by a value set in TF_SLP[31:0]

is set using the TF_ATK[31:0] register bits. A maximum attenuation can be specified using register bits

TF_MAX_ATN[31:0]. However, if the device continue to heat up, eventually the device over-temperature will

be triggered. The attenuation will be held for a number of samples set by register bits TF_HLD[31:0], before the

attenuation will begin releasing.

8.4.7 Over Power Protection

The TAS2781 monitors the temperature of the internal power FETs. If the maximum continue power is high and

power FETs temperature goes above a threshold, an internal protection circuit will trigger a thermal foldback and,

if temperature still incraeses, shutdown the device.

The protection mechanism is based on two thresholds TH1 and TH2. The TH1 threshold is set at a temperature

116 °C higher than the temperature measured by the internal bandgap but not less than 250 °C. The TH1

threshold triggers a thermal foldback.

The TH2 threshold is 40 °C above TH1 and triggers thermal shutdown.

The two detection mechanisms can be disabled by setting to low the bits TG_TH2 and TG_TH1.

8.4.8 Low Battery Protection

For PVDDL supply below 3.4 V the power FETs can go into saturation at higher load currents which could result

in device damage due to the FETs connected to PVDDH going into thermal runaway.

To prevent the damage the OCP limit is adjusted based on PVDDL level measured by the internal SAR ADC.

The table below presents the PVDDL thresholds where the OCP will be adjusted automatically. Lower PVDDL

level will correspond to lower OC limit setting.

Table 8-4. PVDDL Range and Thresholds

PVDDL Range

PVDDL ≥ 3.4 V

3.1 V ≤ PVDDL < 3.4 V

2.9 V ≤ PVDDL < 3.1 V

2.7 V ≤ PVDDL < 2.9 V

The control of OC limit occurs in power modes where PVDDL is supplied externaly and the output is switching

on PVDDH (PWR_MODE0, PWR_MODE1).

8.4.9 Battery Power Limiter

The TAS2781 integrates an algorithm that can control the audio power by regulating the current based on the

battery voltage readout.

The algorithm provides three levels of current based on two levels of battery voltage.

www.ti.com

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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