TAS2781RYYR datasheet(21/90 Pages) TI2

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playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right

time slot or stereo down mix set by the RX_SLOT_R[3:0] and RX_SLOT_L[3:0] register bits.

If time slot selection places reception either partially or fully beyond the frame boundary, the receiver will return a

null sample equivalent to a digitally muted sample.

The TDM port can transmit a number of sample streams on the SDOUT pin: speaker voltage sense, speaker

current sense, interrupts and status, PVDDH voltage and die temperature.

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be

configured by setting the TX_EDGE register bit. The TX_OFF[2:0] register bits define the number SBCLK cycles

between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for

Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the

setting of the TX_FILL register bit. An optional bus keeper will weakly hold the state of SDOUT pin when all

devices are driving Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via

the TX_KEEPEN register bit. The bus keeper can be configured to hold the bus for only 1 LSB or Always

(permanent) using TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of

cycle using TX_KEEPCY register bit.

TX_FILL is used in mono system where there is only one amplifier on I2S bus. All the slots unused by the

amplifier will be filled with zeros when TX_FILL is set to low. The TX bits mentioned are in the register in .

The SDOUT_HIZ registers from page 0x01 are useful when multiple devices are on the same I2S bus. Each

device does not know configuration of slots in the other devices on the bus. It is required at the system level

to program the SDOUT_HIZ registers appropriately, in such way that the settings are done correctly and do not

create any contention both internally and externally.

The current and voltage values are transmitted at the full 16-bit measured values by default. The

IVMON_EN[1:0] bits of register from can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits

values across multiple slots. The special 12-bit mode is used when only 24-bit I2S/TDM data can be processed

by the host processor. The device should be configured with the voltage-sense slot and current-sense slot off

by 1 slot and will consume 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits

followed by the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at

the frame boundary.

The time slots for SAR measurements (PVDDL, PVDDH and temperature) are set using SAR_DATA_SLOT[5:0]

by bit SAR_DATA_SL of register from .

For TDM final processed audio slot, enable and length settings use AUDIO_SLOT[5:0], AUDIO_TX and

AUDIO_SLEN register bits.

Information about status of slots can be find in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set

high enables the status transmit.

8.4.2 Playback Signal Path

8.4.2.1 Digital Signal Processor

An on-chip, low latency DSP supports Texas Instrument Smart Amp speaker protection algorithms to maximize

loudness while maintaining safe speaker conditions.

The DSP also features Band EQ, stereo balancing, ultrasound and external boost controller for Class-H amplifier

operation.

8.4.2.2 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The

TAS2781 employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. The

HPF_FREQ_PB[2:0] register bits set the corner frequencies of HPF. The filter can be bypassed by setting the

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TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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