TAS2781RYYR datasheet(33/90 Pages) TI2

33 / 90 page

Note

It is mandatory to have TDM clocks available before programming I2C to enter Active mode. Entering

Active mode with no clocks present will trigger a clock error, device will go into software shutdown and

the interrupts associated with the clock errors will be raised.

The TAS2781 also monitors die temperature and Class-D load current and will enter software shutdown mode

if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults

if the appropriate fault interrupt mask register bit is set low for over temperature and for over current. The fault

status can also be monitored in the latched fault registers as with the TDM clock error.

Die over temperature and Class-D over current errors can either be latching (i.e. the device will enter Software

Shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after

a prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for

over temperature and over current). Even in latched mode, the Class-D will not attempt to retry after an over

temperature or over current error until the retry time period (Default = 1.5 s) has elapsed. This prevents applying

repeated stress to the device in a rapid fashion that could lead to device damage. If the device has been

cycled through SW/HW shutdown, the device will only begin to operate after the retry time period. By default the

RETRY feature is disabled.

The status registers (and IRQZ pin if enabled, and for un-masked interrupts) also indicate limiter behavior

including when the limiter is activated, when PVDDH is below the inflection point, when maximum attenuation

has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

In the situations when the device operates in PWR_MODE2 the PVDDL pin is supplied by an internal LDO.

Protection circuits monitor this block and generate faults in case of under voltage, over voltage or if the LDO is

over loaded. The device goes into shut down if one of these faults triggers.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be

pulled up with a resistor to IOVDD. An internal 20 kΩ pull up resistor is provided. It can be accessed by setting

the IRQZ_PU register bit of Register 0x04 to high.

The IRQZ interrupt configuration can be set using IRQZ_CFG[1:0] register bits in Register 0x5C. The IRQZ_POL

register bit sets the interrupt polarity and IRQZ_CLR register bit allows to clear all the interrupt latch register bits.

Live flag registers are active only when the device is in Active mode of operation. If the device is in Software

Shutdown by I2C command or due to any fault condition described below, the live flags will be reset. Latched

flags will not be reset in this condition and available for user to read their status.

Table 8-8. Fault Interrupt Mask

Interrupt

Live Register

Latch Register

Mask Register

Default (1 = Mask)

Temp Over 105 ºC

IL_TO105

IR_TO105

IM_TO105

Temp Over 115 ºC

IL_TO115

IR_TO115

IM_TO115

Temp Over 125 ºC

IL_TO125

IR_TO125

IM_TO125

Temp Over 135 ºC

IL_TO135

IR_TO135

IM_TO135

Over Temp Error

Device in shutdown

IR_OT

IM_OT

Over Current Error

Device in shutdown

IR_OC

IM_OC

TDM Clock Error

Device in shutdown

IR_TDMCE

IM_TDMCE

TDM Clock Error: Invalid SBCLK ratio or FS

rate

IR_TDMCEIR

TDM Clock Error: FS changed on the fly

IR_TDNCEFC

TDM Clock Error: SBCLK FS ratio changed on

the fly

IR_TDMCERC

BOP Active

IL_BOPA

IR_BOPA

IM_BOPA

BOP Infinite Hold

IL_BOPIH

IR_BOPIH

IM_BOPIH

BOP Mute

IL_BOPM

IR_BOPM

IM_BOPM

BOP Detected

IL_BOPD

IR_BOPD

IM_BOPD

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TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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