TAS2781RYYR datasheet(32/90 Pages) TI2

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A software reset can be accomplished by setting high the SW_RESET register bit. This bit is self clearing. Once

enabled it will restore all registers to their default values.

8.5.4 Software Shutdown

Software Shutdown mode powers down all analog blocks required to playback audio, but does not cause the

device to lose register state.

The registers are available through I2C or SPI interface.

Software Shutdown is enabled by asserting the MODE[2:0] register bits to 3'b010. If audio is playing when

Software Shutdown is asserted, the Class-D will volume ramp down before shutting down. When de-asserted,

the Class-D will begin switching and volume will ramp back to the programmed digital volume setting.

8.5.5 Mute Mode

The TAS2781 will ramp down volume of the Class-D amplifier to a mute state by setting the MODE[2:0] register

bits to 3'b001. During mute the Class-D still switches but transmits no audio content. If mute is de-asserted, the

device will ramp volume back to the programmed digital setting.

8.5.6 Active Mode

In Active Mode the Class-D switches and plays back audio. Speaker voltage and current sensing are operational

if enabled. Set the MODE[2:0] register bits to 3'b000 to enter Active Mode.

8.5.7 Noise Gate Mode

In this mode of operation described in section Section 8.4.2.8 the device monitors the signal and powers down

the Class-D when signal goes below a threshold.

8.6 Faults and Status in TAS2781

During the power-up sequence, the circuit monitoring the AVDD pin (UVLO) will hold the device in reset

(including all configuration registers) until the supply is valid. The device will not exit Hardware Shutdown

until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will

power up, enabling detection of the operational mode. If AVDD dips below the UVLO threshold, the device will

immediately be forced into a reset state.

The device also monitors the PVDDH supply and holds the analog core in power down if the supply is below the

UVLO threshold (set by register bits PVDDH_UV_TH[5:0]). If the TAS2781 is in active operation and an UVLO

fault occurs, the analog blocks will immediately be powered down to protect the device. These faults are latched

and require a transition through HW/SW shutdown to clear the fault. The latched registers will report UVLO

faults.

When exiting Software Shutdown to Active (for example: MODE[2:0] bits from 010b to 000b), if PVDDH

undervoltage is detected, the device will go back into Software Shutdown and an interrupt (IL_PUVLO) will

be flagged. To exit this fault user needs to clear the interrupt and program the device in Software Shutdown

using MODE[2:0] bits, before making another attempt to go to Active mode.

A similar situation might occur in PWR_MODE2, if internal PVDDL LDO undervoltage is detected and

IL_LDO_UV interrupt is flagged.

The device transitions into Software Shutdown mode if it detects any faults with the TDM clocks such as:

• Invalid SBCLK to FSYNC ratio

• Invalid FSYNC frequency

• Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into Software Shutdown mode as quickly as possible

to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back

to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt

mask register bit IM_TDMCE is set low. The clock fault is also available for read-back in the live or latched fault

status registers (bits IL_TDMCE and IR_TDMCE).

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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