TAS2781RYYR datasheet(31/90 Pages) TI2

31 / 90 page

Note

When using the external boost controller the supply tracking limiter should be either disabled or have

the thresholds programmed to a value higher than maximum output voltage of the boost.

To program the internal Class-H controller use registers from pages 0x05 and 0x06.

See TAS2781 User Manual and SLOA326 Application Note for more details on programming the boost

controller.

8.5 Operational Modes

8.5.1 Beep Generator

This tone generator produces a simple audio tone (beep) that is transmitted directly to the output (speaker).

The generator relies on a pulsed signal coming into either SDZ or NC_SCLK pin.

The beep generation is executed by pulsating any of these two pins with an input frequency fIN specified in .

The beep output signal will have a frequency given by:

fBEEP = fIN/64 for SDZ pin;

(3)

fBEEP = fIN/4 for NC_SCLK pin.

(4)

For example, if an 800 Hz beep is needed, input a 3.2 kHz PWM signal to pin NC_SCLK.

The beep generation can happen when the device is in Software Shutdown mode, by applying pulses on the

pin. A deglitch timer will hold-off the shut-down functionality until the tone has finished and the deglitch timer has

expired in which case the pin will revert to controlling the hardware shutdown of the device (SDZ) or SPI clock

(NC_SCLK).

The output power of the beep signal is controled by the duty cycle of the input signal as discribed in the table

below.

Table 8-7. Beep Output Power

Load (Ω )

Duty Cycle (% )

Ouput Power ( W )

20 - 30

0.125

45 - 55

0.25

70 - 80

0.5

Note: When NC_SCLK pin is used for beeping, pin 17 should be connected to an 1.8 V supply (AVDD, IOVDD).

8.5.2 Hardware Shutdown

The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode,

the device consumes the minimum quiescent current from AVDD, IOVDD, PVDDH and PVDDL supplies. All

registers lose state in this mode and I2C or SPI communication is disabled.

By default, when SDZ pin goes low, the device will force a hardware shutdown after a timeout set by the

configurable shutdown timer (register bits SDZ_TIMEOUT[1:0]). If SDZ is asserted low while audio is playing, the

device will ramp down volume of the audio, stop the Class-D switching, power down analog and digital blocks

and finally put the device into Hardware Shutdown mode. The device can also be configured for forced hardware

shutdown and in this case it will not attempt to gracefully disable the audio channel. The shutdown mode can be

controlled using SDZ_MODE[1:0] register bits.

When SDZ is released, the device will sample the ADDR pin and enter the Software Shutdown mode.

8.5.3 Mode Control and Software Reset

The TAS2781 mode can be configured by writing the MODE[2:0] register bits.

www.ti.com

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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