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TAS2781RYYR датащи(PDF) 52 Page - Texas Instruments |
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TAS2781RYYR датащи(HTML) 52 Page - Texas Instruments |
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52 / 90 page ![]() Bit Field Type Reset Description 5-3 CLK_HALT_TIMER[2:0] RW 3h Clock halt timer values 0h = 820 μs 1h = 3.27 ms 2h = 26.21 ms 3h = 52.42 ms (default) 4h = 104.85 ms 5h = 209.71 ms 6h = 419.43 ms 7h = 838.86 ms 2 IRQZ_CLR RW 0h Clear interrupt latch registers 0h = Do not clear 1h = Clear (self clearing bit) 1-0 IRQZ_CFG[1:0] RW 1h IRQZ interrupt configuration. IRQZ will assert 0h = On any unmasked live interrupt 1h = On any unmasked latched interrupt (default) 2h = For 2 - 4 ms one time on any unmasked live interrupt event 3h = For 2 - 4 ms every 4 ms on any unmasked latched interrupt 8.9.54 Page = 0x00 Address = 0x5D [Reset = 80h] Bit Field Type Reset Description 7 IRQZ_POL RW 1h IRQZ pin polarity 0h = Active high 1h = Active low 6-0 Reserved R 00h Reserved 8.9.55 Page = 0x00 Address = 0x60 [Reset = 0Dh] Bit Field Type Reset Description 7-2 SBLK_FS_RATIO[5:0] RW 3h SBCLK to FS ratio when AUTO_RATE=1 (disabled). See Table 8-9. 1-0 Reserved R 1h Reserved Table 8-9. SBCLK to FSYNC Ratio (AUTO_RATE=1) 00h = 16 01h = 24 02h = 32 03h = 48 (defaut) 04h = 64 05h = 96 06h = 128 07h = 192 08h = 256 09h = 384 0Ah = 512 0Bh = 125 0Ch = 250 0Dh = 500 0Eh - 3Fh = Reserved 8.9.56 Page = 0x00 Address = 0x63 [Reset = 48] Bit Field Type Reset Description 7 IDLE_IND RW 0h Idle channel optimization 0h = Used for inductors ,15 μH and higher 1h = Used for 5 μH inductors 6-0 Reserved R 48h Reserved 8.9.57 Page = 0x00 Address = 0x65 [Reset = 08] Bit Field Type Reset Description 7 PWR_LIM_SRC RW 0h Limiter power source 0h = PVDDL 1h = PVDDH 6-0 Reserved R 08h Reserved TAS2781 SLOSE86B – JULY 2022 – REVISED JULY 2023 www.ti.com 52 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TAS2781 |
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