301020013 datasheet(52/109 Pages) AMSOSRAM

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9.1.5

Control register 3 (Address 0x05)

Table 21: Control register 3

Address: 0x05

Default value: 0x12

Access: Read/Write

Bit

Bit name

Default value

Bit description

7:6

N/A

00b

Not used

5:3

Bandgap Switch

010b

These bits can be used to trim the reference current

generated by the bandgap circuit of different

segments. The bits configuration is shown in

Table 22.

2:2

Enable Offset SRAM(1)

Set to '0' – Offset SRAM is powered down. Stored

offset values are lost.

Set to '1' – Offset SRAM is enabled.

1:1

Re-linearization

Set to '0' – In companding ADC mode the piece wise

linear compressed data is given out.

Set to '1' – When using the companding ADC mode,

the compressed data is re-linearized on chip to a

linear 12 bits representation. It is recommended to

use dithering (control register 0x01 bit 3) together

with this feature to avoid missing codes in the output

signal.

0:0

Pixel Clock Output

Enable

Set to '0' – The pixel clock pad is in tristate mode. No

pixel clock in given out.

Set to '1' – The pixel clock is provided to the user on

the pad.

(1) Feature related to digital subtraction, which is not recommended to be set to ‘1’. Still, if using this feature, it is at user’s

responsibility.

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