301020013 datasheet(48/109 Pages) AMSOSRAM

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Every internal status of the sensor will be controlled by the serial interface and be written to the

internal registers. All registers are 8-bit oriented. The unused bits on a register are set to zero

and reserved for future use.

9.1

Detailed register description

9.1.1

Control register 1 (Address 0x01)

Table 16: Control register 1

Address: 0x01

Default value: 0xA8

Access: Read/Write

Bit

Bit name

Default value

Bit description

7:7

VThr Bit

Set to '0' – For test purposes only. Do not use.

Set to '1' – The threshold voltage for the white

clamping is given internally.

6:6

ADC Mode Bit

Set to '0' – Linear ADC conversion is used.

Set to '1' – Companding ADC conversion is used.

5:5

Enable Saturation(1)(2)

Set to '0' – The digital saturation is not enabled, so the

output will cover full 13-bit. If 12 bits are read out

"wrap around" error may occur if End ADC range is

not properly configured.

Set to '1' – Digital saturation is enabled, the output will

be saturated to the 12 LSB's (4095 DN).

4:4

Offset Subtraction(3)

Set to '0' – The digital offset is not subtracted from the

read value.

Set to '1' – The value stored in the offset register is

subtracted from the readout signal.

3:3

Dithering

Set to '0' – Dithering deactivated (for ADC linear

mode).

Set to '1' – Dithering activated (noise generated for

ADC).

This bit enables the on chip dithering logic to avoid

missing codes in the output histogram when on chip

re-linearization is used in combination with

companding ADC mode.

2:2

Clock Division 2

These bits are responsible for the definition of readout

clock (pixel clock), the different values are presented

in Table 17.

1:1

Clock Division 1

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