301020013 datasheet(43/109 Pages) AMSOSRAM

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Dragster

Functional description

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DS000444 • v5-00 • 2025-Aug-29

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7.6.2.5

Load pulse signal generation

The LOAD_PULSE signal is at the sensor side latched with the rising edge of pixel clock, thus

the phase in which it is generated must be adjusted such that at the sensor pin. The

LOAD_PULSE is high only during one rising edge of pixel clock. For low temperatures (below

10ºC) it is recommended to use a pulse width of 2 x Pixel Clock period.

In case of problems with stable LVAL generation (no LVAL generated or LVAL signal not with

the correct length), please change the phase on which the LOAD_PULSE is generated.

Figure 24: LOAD_PULSE signal generated with correct timing(1)

(1) The drawing signals are indicated, as they are present on the pin of the chip.

7.6.3

Dragster sequential/pipeline timing

While in Pipeline mode the next integration is performed after the previous one, during A/D

conversion and Readout, the Sequential mode, as the name refers, each stage of Integration,

A/D conversion and Readout are done sequentially, not in parallel with the other timing stages.

Figure 25: Dragster sequential timings

Pixel Clock

Load_Pulse

Reset

CVC

Reset

CDS

Integration I

Reset

CVC

Conversion I

Sample

Start AD

Start

Readout

Readout I

Reset

CDS

Integration I+1

Conversion I+1

Sample

Start AD

Start

Readout Readout I+1

Integration I+2

Conversion I+2

Sample

Start AD

Start

Readout Readout I+2

Reset

CVC

Reset

CDS

Scan I

Scan I+1

Scan I+2

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