301020013 datasheet(41/109 Pages) AMSOSRAM

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Functional description

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SAMPLE Signal Timing:

•

SAMPLE rising edge must follow below rules:

– Occur at least 1 µs after RST_CDS falling edge.

– Occur at least 1 clock cycle after END_ADC goes HIGH.

Two configuration options for SAMPLE pulse width are available:

1. Fixed Pulse Width (1 µs):

– The entire SAMPLE pulse (rising and falling edges) is shifted in time to adjust when the

integration ends, having in consideration the respective timing rules.

2. Variable Pulse Width:

– Both SAMPLE rising and falling edges areadjusted to control integration time, having in

consideration the respective timing rules.

– For a minimum integration time of 2 µs, the SAMPLE pulse must remain high for at

least 1 µs.

END_ADC Timing:

•

The END_ADC falling edge occurs 8 clock cycles after SAMPLE falling edge.

LOAD_PULSE Timing:

•

The LOAD_PULSE signal (1 clock cycle) rising edge must occur at least 4 clock cycles

after the later of:

– LVAL falling edge, or

– END_ADC rising edge.

LVAL Timing:

•

The rising edge occurs 8 clock cycles after the LOAD_PULSE falling edge.

7.6.2.1

Idle time

Idle Time consists of:

•

The fixed RST_CDS pulse width (2 µs), plus

•

The interval between the SAMPLE falling edge and RST_CVC/RST_CDS rising edge (≥ 7

clock cycles).

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