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301020013 датащи(PDF) 46 Page - ams-OSRAM AG |
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301020013 датащи(HTML) 46 Page - ams-OSRAM AG |
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46 / 109 page ![]() Dragster Digital interface Datasheet • PUBLIC • Document Feedback DS000444 • v5-00 • 2025-Aug-29 46 / 109 / 8.2 Serial 4-wire configuration interface 8.2.1 General description The SPI interface controls static configuration data, such as operation modes, ADC gain, black level and other special features. It is present in every segment, top and bottom sides. This interface is based on 8-bit registers and addressed using 8-bit addresses. The interface uses the following signals: Table 15: SPI signals Signal DIG In/Out Function MISO Out Master In, Slave Out MOSI In Master Out, Slave In N_CS In Low active chip select SCLK In Serial interface clock For access to the internal registers of the sensor, a serial interface with four wires are implemented. The interface consists in four different lines, one clock line (SCLK), one receive (MOSI) and transmit (MISO) line which are synchronous to each other. The fourth line is the chip select (N_CS) and must be low to send/receive data through the lines. The sensor is always slave in the application. By the use of the N_CS signal, the master can activate the serial interface of an individual segment or several segments together. The bus frequency range is from DC to 20 MHz, but must always be lower than MCLK/2. 8.2.2 Writing operation The writing operation is performed by sending the word containing the data and the address. No acknowledge signal or indication is given back. The data is sent from LSB to MSB. The command word has a length of 16 bits and contains the data of the register and the register address. It is possible to write multiple registers consecutively, sending data and address each 16 SCLK. After the last written word, the SCLK should be sent for minimum of two extra clocks, (maximum 4 SCLK) while N_CS is still low. The updating to the registers is performed after update request bit is sent at the next rising edge of END_ADC signal. The last word sent to the registers has to be always to register 0x01 and containing the update request bit, otherwise the update is not performed. |
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