301020013 datasheet(27/109 Pages) AMSOSRAM

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Functional description

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7.2.2

Anti-corona circuitry

“Corona effect” is a phenomenon sometimes observed under heavy over exposure condition

when the most exposed pixels start to become dark again instead of white. This condition can

be detected by a special circuitry and saturated pixels are then clamped to the white reference

value before A/D conversion. This circuitry can be enabled or bypassed by means of register

0x01 bit '7'. The bit set to ‘0’ will disable the anti-corona circuitry and bypass the signal, while

’1’ will enable it.

7.2.3

Analogue gain

The pixel features a programmable analogue gain of factor x4 at CDS stage level. This gain is

controlled by register 0x02 bit '5'. The bit set to ‘0’ unity gain is set and ’1’ sets the gain to x4.

7.2.4

CDS reference generation

The reference voltage for all CDS stages is generated in parallel by the internal bias

generation block. The power consumption of the driver to this voltage can be regulated by

means of register 0x02 bit '1'. A value of ‘1’ will use an adaptive bias scheme to the buffer for

this voltage, which will reduce power consumption when this driver is not used

(recommended). A ‘0’ will choose a fixed bias value, which will result in a higher overall

consumption.

The reference voltage of the CDS stage is sampled at start of integration for each line, and

thus influences the finally digitized analogue value. Any noise on this signal also influences the

final signal value as noise will be added equally to all pixels in the line. For ultimate noise

performance, it is advised to compute the average of the first dark pixels 16th to 20th and

subtract this value from the finally read out pixels for each line. This computation has to be

done off chip, but will lead to better noise performance than the one specified.

7.2.5

Analogue voltage references

The analogue voltage references, especially the references to define the ADC start voltage

and the ADC gain are interconnected along the sensor line, however, remain individual for odd

an even pixels in the case of 3.5 μm pixels sensors. Each segment comprises an individual

SPI block to configure these voltages. Normally, it is recommended to program the registers

controlling an interconnected voltage with the same settings. The figures below illustrate how

analogue voltages are interconnected over multiple segments and controlled over the

respective SPI interfaces for sensors with 7 μm and 3.5 μm pixel pitch respectively.

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