301020013 datasheet(42/109 Pages) AMSOSRAM

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Functional description

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DS000444 • v5-00 • 2025-Aug-29

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7.6.2.2

Line rate control

For a Fixed Integration Time:

•

The line period (or line rate) is adjusted by changing the interval between the SAMPLE

falling edge and RST_CVC/RST_CDS rising edge.

7.6.2.3

Integration time control

For a Fixed Line Period:

1. If SAMPLE has a fixed 1 µs duration:

•

To increase integration time:

– Move the entire SAMPLE pulse forward, ensuring its falling edge is at least ≥ 7 clock

cycles before the next RST_CVC/RST_CDS rising edge.

•

To decrease integration time:

– Move the entire SAMPLE pulse backward, ensuring a minimum 1 µs interval from

RST_CDS falling edge to the SAMPLE rising edge, a minimum 1 µs SAMPLE pulse

width and SAMPLE rising edge at least 1 clock apart from END_ADC rising edge.

2. If SAMPLE has a variable width:

•

To increase integration time:

– Extend SAMPLE pulse by delaying the falling edge, while maintaining at least ≥ 7 clock

cycle before the next RST_CVC/RST_CDS rising edge, taking in consideration that

SAMPLE rising edge needs always come after END_ADC rising edge.

•

To decrease integration time:

– Advance SAMPLE falling edge, ensuring a minimum 1 µs interval from RST_CDS

failing edge to SAMPLE rising edge, a minimum 1 µs SAMPLE pulse width and

SAMPLE rising edge at least 1 clock apart from END_ADC rising edge.

7.6.2.4

Minimum line period requirement

The line period cannot be shorter than:

•

The total duration of:

– Integration time

– RST_CDS pulse width

– Time between SAMPLE falling edge and RST_CVC/RST_CDS rising edge

•

ADC conversion time

•

LVAL period

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