301020013 datasheet(32/109 Pages) AMSOSRAM

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Dragster

Functional description

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7.4.2

ADC linear mode

On linear conversion the ADC will require as many clock cycles as the register programmed

ADC end of range. Figure 14 shows a diagram of the ADC linear response function and the

effect of the different registers on the transfer function.

Information:

It is important to program the end of range according to the pixel data bit width. If digital

saturation logic is not enabled in the register 0x01 bit '5', ADC end of range is above 4095 DN

and only 12 LSBs are read out, this can create signal “wrap around” artefacts when the pixel

value is over 4095 DN.

In order to reduce the ADC conversion time, comparing to readout time and keep the ADC in

linear mode, the conversion can be operated at a higher clock frequency than the remaining

circuitry. This is done by directly supplying the higher clock frequency to the chip main clock

and programming the internal clock divider (register 0x01 bits 1 and 2) such that the clock

frequency in chip's readout remains below 50 MHz.

Figure 14: ADC transfer function in linear mode and registers defining the ADC parameters

When in linear mode conversion time (CT) is obtained by the Equation below:

Equation 1:

�� = �� × 32 ×

��

ADC End Range

ADC Step

ADC Black Level

Analogue Voltage Range

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